![]() ASIC cell library An ASIC (“a-sick”) is an application-specific integrated circuit A gate equivalent is a NAND gate F = A.The difference between standard-cell, gate-array, and programmable ASICs.Key concepts: The difference between full-custom and semicustom ASICs Text copyright © 1997, 1998 by Michael John Sebastian Smith. ![]() ![]() Figures copyright © 1997 by Addison Wesley Longman, Inc. Where those designations appear in this work, and the author was aware of a trademark claim, the designations have been printed in initial caps or all caps. Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. The author does not offer any warranties, representations, or accept any liabilities with respect to the programs or applications. They have been tested with care but are not guaranteed for any particular purpose. The programs and applications presented in this work have been included for their instructional value. Figures describing Actel FPGAs iare courtesy of Actel Corporation. and foreign patents and patent applications. Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. Altera is a trademark and service mark of Altera Corporation in the United States and other countries. Figures describing Altera CPLDs are courtesy of Altera Corporation. Figures describing Xilinx FPGAs are courtesy of Xilinx, Inc. Information is reprinted with the permission of the IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Some material in this work is reprinted from IEEE Std 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Architecture,” Copyright © 1990 IEEE Std 1076/INT-1991 “IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual,” Copyright © 1991 IEEE Std 1076-1993 “IEEE Standard VHDL Language Reference Manual,” Copyright © 1993 IEEE Std 1164-1993 “IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164),” Copyright © 1993 IEEE Std 1149.1b-1994 “Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,” Copyright © 1994 IEEE Std 1076.4-1995 “IEEE Standard for VITAL Application-Specific Integerated Circuit (ASIC) Modeling Specification,” Copyright © 1995 IEEE 1364-1995 “IEEE Standard Description Language Based on the Verilog® Hardware Description Language,” Copyright © 1995 and IEEE Std 1076.3-1997 “IEEE Standard for VHDL Synthesis Packages,” Copyright © 1997 by the Institute of Electrical and Electronics Engineers, Inc. Smith VLSI Design Series 1,040 pages ISBN 2-1 LOC TK7874.6.S63 Addison Wesley Longman, Additional material (figures, resources, source code) is located at ASICs. the book Application-Specific Integrated Circuits Michael J.
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